Recent advances in the miniaturization of integrated circuits have led to smaller wafer areas made available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet even as the "footprint" (area of a silicon wafer alotted individual memory cells) shrinks, the storage node (capacitor) must maintain a certain minimum charge storage capacity, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve high charge storage per unit area of the wafer. Accordingly, several techniques have been recently developed to increase the total charge capacity of the cell capacitor without significantly affecting the wafer area occupied by the cell.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. An interelectrode dielectric material is deposited between two conductive layers, which form the capacitor plates or electrodes. The amount of charge stored on the capacitor is proportional to the capacitance, C=.epsilon..epsilon..sub.0 A/d, where .epsilon. is the dielectric constant of the capacitor dielectric, .epsilon..sub.0 is the vacuum permittivity, A is the electrode area, and d represents the spacing between electrodes. Some techniques for increasing capacitance include the use of new materials characterized by high dielectric constants.
Other techniques concentrate on increasing the effective surface area ("A") of the electrodes by creating folding structures such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive plates and capacitor dielectric conform. For example, U.S. Pat. No. 5,340,765, issued Aug. 23, 1994 to Dennison et al. and assigned to the assignee present invention, discloses a process for forming a capacitor structure resembling a cylindrical container. More complex structures, such as the container-within-container and multiple pin structures disclosed in U.S. Pat. No. 5,340,763, issued Aug. 23, 1994 to Dennison, may further increase electrode surface area and allow the extension of conventional fabrication materials to future generation memory devices.
Electrode surface area may also be increased by providing a rough texture for the electrode surface. One class of methods for providing rough electrode surfaces involves texturizing a conductive layer by formation of hemispherical grained (HSG) silicon.
FIGS. 1 and 2 illustrate the fabrication of a simple container, including an HSG silicon interior surface, in the context of a dynamic random access memory (DRAM) cell, wherein the container dimensions are defined by etching through a BPSG structural layer 22. The container etch exposes a circuit node 10 which, in the illustrated example, comprises a polysilicon plug 10 in electrical contact with an active area 14 of a semiconductor wafer 16. The plug 10 resides between two neighboring words lines 12 of the DRAM array. A conductive layer 25, generally comprising polycrystalline silicon (polysilicon), is then deposited over the structure, thus lining the inside surfaces of the container 24 as well as forming horizontal arms 26 overlying the structural layer 22. A rugged or rough silicon layer 28 is formed over the polysilicon layer 25 to further enhance the surface area of the in-process container electrode.
Referring now to FIG. 2, the horizontal portions 26 of the polysilicon layer 25 have been removed by a planarization step, such as chemical mechanical planarization (CMP), for electrical isolation of the various memory cells in the array. A polysilicon container 30, which is to serve as a bottom electrode for the cell capacitor, is left in contact with the polysilicon plug 10. An inside surface 42 of the container 30 is available for charge storage during circuit operation. For other known process flows, the outside surface may also contribute to capacitane by removal of the structural layer. The cell's capacitor dielectric and top electrode may then be successively deposited. It should be noted that the illustrated DRAM container cell is but one example of capacitor configurations, and that rugged or rough silicon may increase the electrode surface area of most electrode designs.
The rough silicon 28 may be formed by a number of different methods, including gas phase nucleation and surface seeding. An extremely thin layer of oxide, for example, may serve as a substrate layer for rough silicon growth to follow. Native oxide is allowed to grow over an underlying substrate, such as the polysilicon layer 25 shown in FIG. 1. Polysilicon may then be deposited by low pressure chemical vapor deposition (LPCVD), and silicon grains grow preferentially about nucleation sites. Nucleation sites may also be provided by the deposition of dispersed particles as disclosed by U.S. Pat. No. 5,102,823, issued to Tuttle. In either case, during the initial stages of polysilicon deposition, the presence of nucleation sites causes the formation of polysilicon nodules. During later stages of deposition, polysilicon will continue to coat the previously created nodules, resulting in stable, hemispherical polysilicon grains.
More recently, however, rough silicon has been formed by a surface seeding method. A silicon layer, generally comprising amorphous silicon, is deposited over the electrode substrate (e.g., the polysilicon layer 25 shown in FIGS. 1 and 2). The structure is then subjected to a vacuum anneal within critical temperature and pressure ranges. Thermal energy during the anneal brings about a redistribution of silicon atoms in the amorphous silicon layer, resulting in a rough configuration such as hemispherical grains of polysilicon. U.S. Pat. No. 5,407,534, issued to Thakur and assigned to the assignee of the present invention, discloses a particular texturizing vacuum anneal wherein a fluorine-based gas, diluted with an inert gas (e.g., argon), enhances the redistribution.
The layer of amorphous silicon is heated to a temperature in the range of 560.degree. C. and 620.degree. C., but most efficiently at about 600.degree. C., while the chamber pressure is maintained between about 1.times.10.sup.-1 Torr and 1.times.10.sup.31 3 Torr. A fluorine-based gas (e.g., NF.sub.3, CF.sub.4, or C.sub.2 F.sub.6 Cl.sub.2), diluted with an inert gas (e.g., argon), is bled into the anneal chamber. The amorphous silicon is annealed under these conditions for between 1 minute and 60 minutes. Aside from the incorporation of fluorine-based gas, these parameters are typical of other known vacuum anneal processes for forming rough silicon layers.
A 300 .ANG. layer of amorphous silicon may thus be converted to a layer of rough silicon with grain or "bump height" of about 500 .ANG.. The rough silicon layer 28 forms at least part of surface of the bottom or storage electrode of the memory cell capacitor. Accordingly, in order to provide reasonable conductivity, the rough silicon layer 28 is generally lightly doped with n-type dopants after the anneal step.
Processes of rough silicon fabrication have been shown to result in significantly increased capacitance, which is vital to maintaining the trend toward increasingly dense circuits. At the same time, however, they may increase cost of production considerably. The time required for annealing and post-anneal doping slow down the process as well, reducing throughput. In addition, current methods of fabrication are limited in the "bump height" which can be achieved. Extending the anneal beyond an optimal length of time tends to cause bumps to merge back together.
A need therefore exists to improve the cost and time efficiency of HSG silicon fabrication.